An interconnection for a large-scale system integration (LSI), for example, CPU (central processing unit) and MPU (micro processing unit), and for a silicon semiconductor device, such as a thin-film transistor (abbreviation: TFT) used for a liquid crystal display device (abbreviation: LCD) need to be formed from a low-electrical resistance material having a high electrical conductive characteristic in order to achieve improvements in device properties, such as the reduction of a delay time on signal transmissions. In addition, for example, in a semiconductor memory device such as a NAND-type flash memory, an interconnect technology of a fine structure, for example, an ultrafine structure having a line width of 45 nanometer (unit: nm), 32 nm or 22 nm, is required in order to further increase the memory capacity, or increase the integration density.
In accordance with the development trend of the semiconductor device industry, instead of the conventional aluminum (element symbol: Al), in recent years, a technology which configures an interconnection for LSI or LCD by using a body (interconnection body) mainly formed from copper (element symbol: Cu) has been disclosed. The copper has a higher resistance against the electromigration (abbreviation: EM) and the stressmigration (abbreviation: SM) than Al. (For example, refer to Japanese Unexamined Patent Application Publication No. 61-294838, Japanese Unexamined Patent Application Publication No. 63-156341, Japanese Unexamined Patent Application Publication No. 01-202841, Japanese Unexamined Patent Application Publication No. 02-050432, Japanese Unexamined Patent Application Publication No. 05-047760, Japanese Unexamined Patent Application Publication No. 11-087349, and Japanese Unexamined Patent Application Publication No. 2007-81113).
As a method for forming a copper interconnection including an interconnection body made from Cu, which has a higher electrical conductivity than Al, there has been a conventionally known method for forming a copper interconnection. The method uses a copper alloy including various metal elements as additional elements. For example, there is a method for forming a copper interconnection by using a copper alloy (Cu—Mg alloy) which includes magnesium (element symbol: Mg) as an additional element. (For example, refer to Japanese Unexamined Patent Application Publication No. 11-054458, Japanese Unexamined Patent Application Publication No. 11-186273, and Japanese Unexamined Patent Application Publication No. 2006-24968). In addition, there is a method for forming a copper interconnection by using a copper alloy which includes silver (element symbol: Ag), zirconium (element symbol: Zr), cadmium (element symbol: Cd), or chromium (element symbol: Cr). (For example, refer to Japanese Unexamined Patent Application Publication No. 02-050432, Japanese Unexamined Patent Application Publication No. 59-043570, Japanese Unexamined Patent Application Publication No. 02-062035 and Japanese Patent No. 3220760). For example, there is a method for forming a copper interconnection by using a Cu—Sn alloy which includes tin (element symbol: Sn) as an additional element. (For example, refer to Japanese Unexamined Patent Application Publication No. 02-050432 and Japanese Unexamined Patent Application Publication No. 2007-72428).
A copper interconnection, which is made from a copper alloy as its material, and which is used for LCD, for example, is formed on a glass substrate containing silicon (element symbol: Si) and oxygen (element symbol: O). In addition, for example, a copper interconnection having a damascene structure, which is used for LSI, is generally formed on an interlayer insulating film structured by an oxide layer containing silicon and oxygen, and formed on a silicon (Si) substrate. (For example, refer to Japanese Unexamined Patent Application Publication No. 2007-059660). For example, a copper interconnection is formed on silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide. (Al2O3) or a phospho silicate glass (for example, refer to Japanese Unexamined Patent Application Publication No. 02-050432) or formed on an oxide insulated layer, which contains silicon and oxygen, such as silicon carbide oxide (SiOC), silicon fluoride oxide (SiOF) (for example, refer to Japanese Unexamined Patent Application Publication No. 2005-277390) or porous silica (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-266178) in order to achieve an electrical isolation between the copper interconnection and the silicon substrate.
When a copper interconnection is formed on an oxide layer by using a copper alloy as its material, it is required to prevent an element constituting the oxide layer, such as silicon, from diffusing into the copper interconnection body in order to obtain the copper interconnection having an excellent conductive characteristic with a low electrical resistance value. In addition, in order to avoid the degradation of the electronic insulation characteristics of the oxide layer, it is required to prevent copper, which constitutes the interconnection body, from diffusing into the oxide layer. In the conventional technology, a structure, in which a barrier layer is formed between the oxide layer and the copper interconnection body, is adopted so as to capture the silicon and the copper, which are diffusing, in order to prevent the silicon or the copper from diffusing into the copper interconnection body or the oxide layer. (For example, refer to Japanese Unexamined Patent Application Publication No. 01-202841). The barrier layer is formed from rare metals such as rhenium (element symbol: Re) (refer to Japanese Unexamined Patent Application Publication No. 2007-096241), tantalum (element symbol: Ta) (refer to Japanese Unexamined Patent Application Publication No. 2004-266178 and Japanese Unexamined Patent Application Publication No. 2001-044156), tantalum nitride (TaN) or titanium nitride (TiN) (refer to Japanese Unexamined Patent Application Publication No. 11-186273, Japanese Unexamined Patent Application Publication No. 2004-266178, and Japanese Unexamined Patent Application Publication No. 2000-068269), and tungsten (element symbol: W) (refer to Japanese Unexamined Patent Application Publication No. 2004-266178 and Japanese Unexamined Patent Application Publication No. 2001-044156), tungsten nitride (element symbol: WN) (refer to Japanese Unexamined Patent Application Publication No. 11-186273, Japanese Unexamined Patent Application Publication No. 2004-266178 and Japanese Unexamined Patent Application Publication No. 2000-068269).
There is another known technique for forming a copper interconnection. The technique uses a copper alloy including an additional element which results in forming a barrier layer by itself by reacting with oxygen or silicon constituting the oxide layer. Therefore this technique does not form a barrier layer from conventional tantalum or tantalum nitride. (For example, refer to Japanese Unexamined Patent Application Publication No. 2005-277390). As the additional element “which forms the barrier layer by itself”, manganese (element symbol: Mn) is known. Therefore, a method for forming a copper interconnection is disclosed in which a Cu—Mn alloy which includes manganese as the additional element is used. (Refer to Japanese Unexamined Patent Application Publication No. 2007-059660, Japanese Unexamined Patent Application Publication No. 02-119140, Japanese Unexamined Patent Application Publication No. 06-140398, Japanese Unexamined Patent Application Publication No. 06-310509, WO 2006/025347A1, and WO 2007/100125A1).
For example, a copper interconnection for LSI is usually formed by filling a barrier layer and a copper interconnection body in a narrow trench portion which has an opening width perforated on an insulating film. The insulating film is referred to as an interlayer insulating film. In order to increase the integration degree of LSI, it is imperative to decrease a line width of an interconnection groove opening such as a trench or a contact hole, and to form a copper interconnection having a thin line width.
However, the more the line width of the interconnection is decreased, the more the ratio, which is made up by the barrier layer, is increased. Therefore, there is a problem that the electrical resistance of the resulting interconnection body is unnecessarily increased.
For example, in case when the ratio of the barrier layer in the interconnection formed on the SiOC oxide layer as an inner wall of a fine trench or hole portion, increases, such a problem occurs that the copper interconnection body having a low resistance-value cannot be stably obtained, and which results in trouble to prevent the increase of the integration degree of LSI. In addition, for example, in LCD, especially in a large LCD which needs a long interconnection, there is a disadvantage that the delay of the transmission signal occurs.
Meanwhile, in case when the thickness of the barrier layer is made thinner than the current condition, a sufficient barrier characteristic against the copper diffusion from the interconnection cannot be secured, therefore, the insulation characteristics of the interlayer insulating film cannot be secured, because the copper diffuses into the insulating film side. In addition, the resistance of the interconnection side becomes higher, because the silicon in the insulating film side diffuses toward the interconnection side by the counter diffusion. Therefore, in the current condition, it is difficult to reduce the thickness of the barrier layer further.
Here, for a copper interconnection which has a line width of 32 nm, which is expected to be the interconnection rule for next-generation silicon LSIs, a preferable thickness of the barrier layer is about 3.5 nm so as to obtain the copper interconnection body having a low electrical resistance value and to prevent the degradation of the insulation characteristics of the insulating film due to the diffusion of copper.
The present invention is provided to solve the problems described above. An object of the present invention is to provide a copper interconnection, a semiconductor device and a method for forming the copper interconnection. The copper interconnection, the semiconductor device and the method for forming the copper interconnection can hold a sufficient barrier property against the diffusing copper from the interconnection body side or the diffusing silicon from the insulating film side, and can secure the insulation characteristic of the insulating film as well as to realize the low electrical resistance value of the interconnection, even through the barrier layer is thinner. Accordingly, the copper interconnection, the semiconductor device and the method for forming the copper interconnection can decrease the line width of the interconnection and improve the integration degree of LSI.